F. He and C. M. Tan. “Circuit level interconnect reliability study using 3D circuit model,” Microelectronics Reliability, vol. 50, no. 3, pp. 376-390, 2010
https://www.sciencedirect.com/science/article/pii/S0026271409004375
F. He and C. M. Tan. “Circuit level interconnect reliability study using 3D circuit model,” Microelectronics Reliability, vol. 50, no. 3, pp. 376-390, 2010
https://www.sciencedirect.com/science/article/pii/S0026271409004375